Computer Elements for the 80's

The keynote panel discussion for the June 1978 Computer Elements Workshop focused on the implications of increased scale of integration in devices for the computer business. Sessions at the workshop, sponsored by the IEEE Computer Society's Technical Committee on Computer Elements, examined trends in memory, LSI design, emerging logic technologies, packaging, and testing. Device designers see a continuing trend to larger scales of integration. Simultaneously, speed-power improvements are forecast. The challenge to the device people is to curtail the costs of designing and testing ever more complex chips. There is a concern that reliability might suffer as the chips become more complex. The increased scale of integration is being exploited rapidly by the designers of terminals, minicomputers, and other microprocessor applications. Of course, high-density semiconductor memory is being exploited widely. Designers of large central processors are less certain of how to exploit the increasing scale of integration. Since the major objective for a central processor is speed, the emphasis is on high-performance devices, possibly using several microprocessors in parallel to achieve high throughput. But since the power of this technique is unproven, CPU designers are exploiting modular gate-array or master-slice techniques in high performance configurations. These modular techniques allow a variety of configurations with modest design and testing costs. Memory trends